The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

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It is recomended that the source resistance not exceed 5kohms for operation at 1.

The datashet must remain stable while it is being sampled and should contain little noise. The other files are enabled register, a register, and a multiplexer.

Top rail of Reference voltage. Begin by downloading the files into your desired destination directory and then compile them in this order. Once loaded the multiplexer sends the appropriate channel to the converter on the datashete. Modification to the source code are required to use more than just four channels.

ADC Technical Data

It can be tied to the Start line if the clock is operated under kHz. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins.

The ALE should be pulsed for at least ns in order for the addresses to adc8009 loaded properly. It is the MSB of the select lines.

Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals. See table 1 for details. Be sure to consult the manufactures data-sheets for other chips. If Vcc and ground are used as reference voltages, they should be isolated by decoupling with a dahasheet microF capacitor.


All of the signals are explained below. Address Lines Because the chip has an 8 dataasheet multiplexer there are three address select lines: Signal from the ADC. There are 8, 8 clock cycle periods required in order to complete an entire conversion. Source code The source code consists of a few of files.

Bottom rail of Reference voltage. The signal goes low once a conversion is initiated by the start signal and datashset low until a conversion is complete. It is the Second bit of the select lines. It goes low when a conversion is started and high at the end of a conversion. Start The purpose of the start signal is two fold.

National Semiconductor

Clock The clock signal is required to cycle through the comparator stages to do the conversion. The following control signals are used dztasheet control the conversion.

Up to 72 if the start signal is received in the middle of an 8 clock cycle period. This is an address select line for the multiplexer. As with all control signals it is required to have an input value of Vcc – 1. The clock should conform to the same range as all other control signals. This is a bit of the digital converted output.

The OE signal should conform to the same range as all the other control signals. It is a pulse of at least ns in width. The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA. All control signals should have a high voltage from Vcc – 1.


It is a control signal from the FPGA, which tells the converter when to start a conversion. The start signal should conform to the same range as all other control signals. You will also need to download multiplex. Users can look for a rising edge transition. That is because ADCs require clocking and can contain control logic including comparators and registers.

The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled.

Like the ALE pulse the minimum pulse width is ns. The voltage level that, when received as an input, will output “” to the FPGA. The maximum frequence of the clock is 1. The maximum clock frequency is affected by the source impedance of the analog inputs.

On the rising edge of the pulse the internal datasheer are cleared and on the falling edge of the pulse the conversion is initiated. This means it must remain stable for up to 72 clock cycles. This means that an entire conversion takes at least 64 clock cycles. C is the most significant bit and A is the least. A, B, and C. Note that it can take up to 2. Table 2 provides a summary of all of the input and datasheett to the chip.

There are a couple of limitations that follow: